1. Field of the Invention
This application relates to clock generation in high speed systems and more particularly to generation of clocks when a reference signal used in generating those clocks is lost.
2. Description of the Related Art
High speed communication systems require high speed clocks for transmission and reception of information. For example, in optical communication systems, line cards compliant with standards such as Synchronous Optical Network (SONET) or Synchronous Digital Hierarchy (SDH) (the European counterpart to SONET), utilize clock generation circuits to generate high speed clocks used in data transmission and reception. In a typical clock generation circuit in such SONET (or SDH) compliant systems, a phase-locked loop (PLL) receives a synchronization input reference clock and generates one or more high speed clocks suitable for use in transmitting or receiving data. According to one aspect of such a communication system, when the synchronization input reference clock is lost, the system enters a mode known as “holdover” mode and outputs a clock based on a previously valid reference clock signal.
The accuracy with which the clock generation circuit provides the clock in holdover mode is typically specified in the SONET or SDH standards. For example, GR-1244-CORE specifies Stratum 3 holdover initial frequency error at ±50×10−9 (0.05 ppm). The clock generation circuit tries to maintain the output clock during holdover mode at a frequency based on a previous reference clock signal. While generating the clock in holdover mode, the phase-locked loop typically no longer uses feedback to generate the output clock. However, the clock generated in holdover mode may still drift to such an extent as to fail to meet the holdover requirements. For example, certain phase-locked loops may find it difficult to meet holdover requirements because the voltage controlled oscillators utilized in such systems have too much frequency variation over temperature (e.g., 100 ppm/° C.). In addition, certain phase-locked loops, for example, phase-locked loops using digital techniques as described in application Ser. No. 09/902,541, filed Jul. 10, 2001, entitled “Digitally-Synthesized Loop Filter Circuit Particularly Useful for a Phase-Locked Loop”, find it difficult to meet the initial accuracy required when first entering holdover due to truncation error.
It would be desirable to provide techniques that improve accuracy of clocks generated in holdover mode by, e.g., reducing susceptibility to frequency drift.